Verilog-mode - 안쓰는 output port 처리

그냥 비워둬도 되지만, unused__module__시그널명 이런형태로 변수를 만들어 두고 싶다면, 아래와 같이 지정하면 된다.

 

How do I use AUTOINST to tie off unused ports?

Configure your lint program to ignore signals with a certain naming, such as those with unused in the name, then use AUTO_TEMPLATE to make a unique name for each port.

/* InstModule AUTO_TEMPLATE (
   .out_signal   (unused__@"vl-cell-name"__@"vl-name"[]),   // [] is dropped for single-bit widths
   .out_bus      (unused__@"vl-cell-name"__@"vl-name"[]),   // [] expands to bus range
   .in_signal    ({@"vl-width"{1'b0}}),                     // tie off to zeros
   .in_bus       ({@"vl-width"{1'b1}}),                     // tie off to ones
   .in_bus_SV    ('0),                                      // tie off - if using SystemVerilog
); */
InstModule instname
  (/*AUTOINST*/
   // Outputs
   .out_signal   (unused__instname__out_signal),
   .out_bus      (unused__instname__out_bus[63:0]),
   // Inputs
   .in_signal    ({1{1'b0}}),
   .in_bus       ({64{1'b1}}),
   .in_bus_SV    ('0));