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IT/ASIC | FPGA

Process-Voltage-Temperature (PVT) Variations and Static Timing Analysis

참고글 소개, 너무 기술적인 내용이라 읽기는 싫지만 가끔은 찾아봐야 함

(http://asic-soc.blogspot.kr/2008/03/process-variations-and-static-timing.html)

Sources of variation can be:

  1. Process variation (P)
  2. Supply voltage (V)
  3. Operating Temperature (T)

The best and worst design corners are defined as follows:

  • Best case: fast process, highest voltage and lowest temperature 빠른 공정, 높은 전압, 낮은 온도
  • Worst case: slow process, lowest voltage and highest temperature 늦은 공정, 낮은 전압, 높은 온도
몰라도 걍 본다 생각하자~ ^^