IT/ASIC | FPGA 2017. 8. 7.
Timing sign-off corner
Timing sign-off cornerLet us say, each minima/maxima in cell characteristics as ‘PVT corner’ and net characteristics as ‘extraction corner’. Each combination of PVT extraction corners is referred to as a ‘timing corner’ as it represents a point where timing will be extreme. http://vlsiuniverse.blogspot.kr/2014/01/timing-corners-dimensions-in-timing.html
IT/ASIC | FPGA 2017. 5. 26.
Process-Voltage-Temperature (PVT) Variations and Static Timing Analysis
참고글 소개, 너무 기술적인 내용이라 읽기는 싫지만 가끔은 찾아봐야 함(http://asic-soc.blogspot.kr/2008/03/process-variations-and-static-timing.html)Sources of variation can be:Process variation (P)Supply voltage (V)Operating Temperature (T)The best and worst design corners are defined as follows:Best case: fast process, highest voltage and lowest temperature 빠른 공정, 높은 전압, 낮은 온도Worst case: slow process, lowest voltage and hig..
